1. Field of the Invention
The present invention relates to a method of manufacturing a memory device having improved erasing characteristics, and more particularly, to a method of manufacturing a memory device in which an atmospheric gas and an annealing temperature are controlled so that a blocking oxide layer can maintain a negative voltage during a process for forming the memory device.
2. Description of the Related Art
The development of semiconductor memory devices has focused on increasing storage capacity while, at the same time, increasing programming and erasing speeds. A typical semiconductor memory array structure includes a plurality of memory unit cells connected by circuitry and can be classified as a non-volatile memory device in which information is retained when the power removed or as a volatile memory device such as a dynamic random access memory (DRAM) in which information is retained only while power is applied. The information storage capacity of the memory device is proportional to the integration density of the memory device. A typical unit cell of a semiconductor memory device includes one transistor and one capacitor.
Recently, new types of semiconductor memory devices having new operation principles have been introduced. For example, semiconductor memory devices having a giant magneto-resistance (GMR) structure or a tunneling magneto-resistance (TMR) structure formed on a transistor have been introduced to utilize magnetic resistance characteristics. Also, new structures of non-volatile semiconductor memory devices, such as a phase change random access memory (PRAM) that utilizes a phase change material to provide a data storage function, and a SONOS device having a tunneling oxide layer, a change storing layer, and a blocking oxide layer, have been introduced.
FIG. 1 is a cross-sectional view of a typical conventional SONOS memory device. Referring to FIG. 1, a first doped region 11a and a second doped region 11b doped with a dopant are formed in a semiconductor substrate 10. A channel region is defined in the semiconductor substrate 10 between the first and second doped regions 11a and 11b. A gate structure is formed on the semiconductor substrate 10 contacting the first doped region 11a and the second doped region 11b. The gate structure has a structure in which a tunneling oxide layer 12, a charge storing layer 13, a blocking oxide layer 14, and a gate electrode layer 15 formed of a conductive material are sequentially formed.
Here, the tunneling oxide layer 12 contacts the first doped region 11a and the second doped region 11b of the semiconductor substrate 10, and charge flowing in the channel region is stored in a trap site of the charge storing layer 13 after the electrons pass through the tunneling oxide layer 12. That is, the information programming of the memory device having the above structure is performed when the electrons pass through the tunneling oxide layer 12 under a voltage applied to the memory device and are trapped in the trap site of the charge storing layer 13.
In the SONOS memory device, the device threshold voltage Vth varies depending on whether the electrons are trapped in the charge storing layer 13. The blocking oxide layer 14 on the charge storing layer 13 blocks electrons from leaking into the gate electrode layer 14 while the electrons are trapped in the trap site of the charge storing layer 13, and blocks charge of the gate electrode layer 14 from being injected into the charge storing layer 13.
The SONOS memory device requires a thin tunneling oxide layer 15 to increase the programming and erasing speed. However, this in turn reduces the information retention characteristics of the device. That is, the retention characteristics and erasing characteristics are in a mutual trade-off relationship in accordance with the thickness of the tunneling oxide layer 12. To improve the inverse proportional relationship between the retention characteristics and the erasing characteristics, control over the characteristics of the blocking oxide layer 14 is needed.
However, to prevent the blocking oxide layer 14 from tunneling electrons from the gate electrode layer 15, a thick blocking oxide layer 14 is desired. However, if the blocking oxide layer 14 is too thick, then control of the characteristics of the channel region by the gate electrode layer 15 is adversely affected.